A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National ...

FDSOI FET allows the threshold voltage ( V t ) to be adjustable (i.e., low-Vt and high-Vt states) by using the back gate bias. Our design utilizes the front and back gates of an FDSOI FET as the input ...

This paper contributes to a better knowledge of the behavior of conventional CMOS and CPL full-adder circuit when low voltage, less delay, low power or small power delay products are of concern.